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sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 1 features ? ultra high speed asynchronous operation ? fully static, no clocks ? multiple center power and ground pins for improved noise immunity ? easy memory expansion with ce\ and oe\ options ? all inputs and outputs are ttl-compatible ? single +3.3v power supply +/- 0.3v ? data retention functionality testing ? cost ef cient plastic packaging ? extended testing over -55oc to +125oc for plastics options marking ? timing 12ns access -12 15ns access -15 20ns access -20 25ns access -25 ? operating temperature ranges military (-55 o c to +125 o c) xt industrial (-40 o c to +85 o c) it ? package(s) ceramic flatpack f no. 307 plastic soj (400 mils wide) dj ceramic lcc ec no. 210 ? 2v data retention/low power l pin assignment (top view) 36-pin psoj (dj) 36-pin clcc (ec) general description the as5lc512k8 is a 3.3v high speed sram. it offers ex- ibility in high-speed memory applications, with chip enable (ce\) and output enable (oe\) capabilities. these features can place the outputs in high-z for additional exibility in system design. writing to these devices is accomplished when write enable (we\) and ce\ inputs are both low. reading is accomplished when we\ remains high and ce\ and oe\ go low. as a option, the device can be supplied offering a reduced power standby mode, allowing system designers to meet low standby power requirements. this device operates from a single +3.3v power supply and all inputs and outputs are fully ttl-compatible. the as5lc512k8dj offers the convenience and reliability of the as5lc512k8 sram and has the cost advantage of a plastic encapsulation. 36-pin flat pack (f) available as military specifications ?mil-std-883 for ceramic ?extended temperature plastic (cots) 512k x 8 sram 3.3 volt high speed sram with center power pinout for more products and information please visit our web site at www.micross.com
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 2 functional block diagram truth table mode oe\ ce\ we\ i/o power standby x h x high-z standby read l l h q active not selected h l h high-z active write x l l d active s n o i t c n u f n i p 8 1 a - 0 as t u p n i s s e r d d a \ e we l b a n e e t i r w \ e ce l b a n e p i h c \ e oe l b a n e t u p t u o o / i 0 o / i - 7 s t u p t u o / s t u p n i a t a d v c c r e w o p v s s d n u o r g c nn o i t c e n n o c o n x = don?t care vcc gnd input buffer 4,194,304-bit memory array 1024 rows x 4096 columns i/o controls column decoder row decoder *power down ce\ oe\ we\ dq8 dq1 a0-a18 *on the low voltage data retention option.
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 3 absolute maximum ratings* voltage on vcc supply relative to vss vcc .........................................................................-.5v to 4.6v storage temperature .....................................-65 c to +150 c short circuit output current (per i/o)?........................20ma voltage on any pin relative to vss........................-.5v to 4.6v maximum junction temperature**..............................+150 c power dissipation ................................................................1w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this speci cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ** junction temperature depends upon package type, cycle time, loading, ambient temperature and air ow, and humidity. electrical characteristics and recommended dc operating conditions (-55 o c < t a < +125 o c & -40 o c < t a < +85 o c ; vcc = 3.3v +0.3%) capacitance max description conditions sym -12 -15 -20 -25 units notes power supply current: operating ce\ < v il ; vcc = max f = max = 1/t rc outputs open i ccsp 80 70 60 55 ma 3, 2 "l" version only i cclp 60 50 40 35 ma power supply current: standby ce\ > v ih , all other inputs < v il , vcc = max, f = 0, outputs open i sbtsp 20 20 20 20 ma "l" version only i sbtlp 15 15 15 15 ma ce\ > vcc -0.2v; vcc = max v in vcc -0.2v; f = 0 i sbcsp 15 15 15 15 ma "l" version only i sbclp 9999ma parameter conditions symbol max units notes input capacitance c i 9pf4 output capactiance co 6 pf 4 t a = 25 o c, f = 1mhz v in = 0
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 4 electrical characteristics and recommended ac operating conditions (-55 o c < t a < +125 o c or -40 o c to +85 o c; vcc = 3.3v +0.3%) description sym -12 -15 -20 -25 units notes min ma x min ma x min ma x min ma x read cycle read cycle time t rc 12 15 20 25 ns address access time t aa 12 15 20 25 ns chip enable access time t ace 12 15 20 25 ns output hold from address change t oh 2222ns chip enable to output in low-z t lzce 2 2 2 2 ns 4, 6, 7 chip disable to output in high-z t hzce 6789ns4, 6, 7 output enable acess time t aoe 6789ns output enable to output in low-z t lzoe 0 0 0 0 ns 4, 6, 7 output disable to output in high-z t hzoe 6789ns4, 6, 7 write cycle write cycle time t wc 12 15 20 25 ns chip enable to end of write t cw 8101213ns address valid to end of write t aw 8101213ns address setup time t as 0000ns address hold from end of write t ah 0000ns write pulse width t wp 10 12 15 15 ns data setup time t ds 6788ns data hold time t dh 1111ns write disable to output in low-z t lzwe 2 2 2 2 ns 4, 6, 7 write enable to output in high-z t hzwe 5 6 7 7 ns 4, 6, 7
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 5 input pulse levels ................................................ vss to 3.0v input rise and fall times .................................................. 3ns input timing reference levels ......................................... 1.5v output reference levels .................................................. 1.5v output load ............................................ see figures 1 and 2 notes 1. all voltages referenced to v ss (gnd). 2. i cc limit shown is for absolute worst case switching of addr, addr\, addr, etc. 3. i cc is dependent on output loading and cycle rates. 4. this parameter is guaranteed but not tested. 5. test conditions as speci ed with the output loading as shown in fig. 1 unless otherwise noted. 6. t lzce, t lzwe, t lzoe, t hzce, t hzoe and t hzwe are speci ed with cl = 5pf as in fig. 2. transition is measured 200mv from steady state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce, and t hzwe is less than t lzwe. 8. we\ is high for read cycle. 9. device is continuously selected. chip enables and output enables are held in their active state. 10. address valid prior to, or coincident with, latest occurring chip enable. 11. t rc = read cycle time. 12. chip enable and write enable can initiate and terminate a write cycle. 13. output enable (oe\) is inactive (high). 14. output enable (oe\) is active (low). 15. asi does not warrant functionality nor reliability of any product in which the junction temperature exceeds 150c. care should be taken to limit power to acceptable levels. fig. 1 output load equivalent fig. 2 output load equivalent data retention electrical characteristics (l version only) ac test conditions description sym min max units notes vcc for retention data v dr 2v data retention current vcc = 2.0v i ccdr 6.5 ma chip deselect to data t cdr 0ns4 operation recovery time t r 20 ms 4, 11 conditions ce\ > v cc -0.2v v in > v cc -0.2 or 0.2v 3.3v q 353 5 pf 319 q 30 pf r l = 50 v l = 1.5v z o =50
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 6 low v cc data retention waveform read cycle no. 1 1, 2 (address controlled, ce\ = oe\ = v il , we\ = v ih ) read cycle no. 2 (we\ = v ih ) don?t care unde ned data retention mode 4.5v 4.5v v dr > 2v v dr t cdr t r v cc ce\ v ih - v il - address t rc t oh t aa previous data valid data valid i/o, data in & out valid address t rc t aoe ce\ t lzoe t ace data valid high-z t hzoe t hzce t pd i/o, data in & out icc t lzce t pu notes: 1. we\ is high for read cycle. 2. device is continuously selected. chip enables and output enables are held in their active state.
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 7 write cycle no. 1 1 (ce controlled) write cycle no. 2 1, 2 (write enabled controlled) address t wc t cw ce\ t aw data valid t ah t as i/o, data out t wp1 t ds t dh we\ i/o, data in high-z high-z address t wc t cw ce\ t aw data valid t ah t as i/o, data out t wp1 t dh we\ i/o, data in high-z high-z notes: 1. chip enable and write enable can initiate and terminate a write cycle. 2. output enable (oe\) is inactive (high).
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 8 write cycle no. 3 1, 2, 3 (we controlled) address t wc t cw ce\ t aw data valid t ah t as data out data unde ned t wp2 t ds t dh t hzwe t lzwe we\ data in high-z notes: 1. at any given temperature and voltage condition, t hzce is less than t lzce , and t hzwe is less than t lzwe . 2. chip enable and write enable can initiate and terminate a write cycle. 3. output enable (oe\) is active (low).
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 9 mechanical definitions* micross case #307 (package designator f) bottom view 36 1 c e2 a q *all measurements are in inches. d e b top view d1 s e l pin 1 identi er area min ma x a 0.096 0.125 b 0.015 0.022 c 0.003 0.009 d 0.910 0.930 d1 0.840 0.860 e 0.505 0.515 e2 0.385 0.397 e l 0.250 0.370 q 0.020 0.045 symbol micross specifications 0.050 bsc
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 10 *all measurements are in inches. mechanical definitions* package designator dj min ma x a 0.128 0.148 a1 0.025 --- a2 0.082 --- b 0.015 0.020 b 0.026 0.032 c 0.007 0.013 d 0.920 0.930 e 0.435 0.445 e1 0.395 0.405 e2 e symbol micross specifications 0.050 bsc 0.370 bsc
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 11 mechanical definitions* micross case #210 (package designator ec) d e pin 1 identi er area l2 l e b r d1 1 36 *all measurements are in inches. a a1 p min ma x a 0.080 0.100 a1 0.054 0.066 b 0.022 0.028 d 0.910 0.930 d1 0.840 0.860 e 0.445 0.460 e l l2 0.115 0.135 p --- 0.006 r 0.009 typ micross specifications symbol 0.050 bsc 0.100 typ
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 12 ordering information *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c 883c = full military processing 1 -55 o c to +125 o c **options definitions l = 2v data retention / low power notes: 1. 883c process available with ceramic packaging only. example: as5lc512k8f-12l/xt device number package type speed ns options** process as5lc512k8 f -12 l /* as5lc512k8 f -15 l /* as5lc512k8 f -20 l /* as5lc512k8 f -25 l /* example: as5lc512k8dj-20l/883c device number package type speed ns options** process as5lc512k8 dj -12 l /* as5lc512k8 dj -15 l /* as5lc512k8 dj -20 l /* as5lc512k8 dj -25 l /* example: as5lc512k8ec-15l/it device number package t yp e speed ns options** process as5lc512k8 ec -12 l /* as5lc512k8 ec -15 l /* as5lc512k8 ec -20 l /* as5lc512k8 ec -25 l /*
sram as5lc512k8 as5lc512k8 rev. 2.2 01/10 micross components reserves the right to change products or speci cations without notice. 13 document title 512k x 8 sram 3.3 volt high speed sram with center power pinout rev # history release date status 2.1 pg 1: changed 0.3% to 0.3v august 2009 release 2.2 updated micross information january 2010 release

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